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CY2305, CY2309
Low Cost 3.3V Zero Delay Buffer
Features

Functional Description
The CY2309 is a low cost 3.3V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY2309 has two banks of four outputs each, which can be controlled by the select inputs as shown in the "Select Input Decoding" table on page 3. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The CY2305 and CY2309 PLLs enter a power down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25.0 A current draw for these parts. The CY2309 PLL shuts down in one additional case as shown in the table below. Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high drive version of the -1, and its rise and fall times are much faster than the -1s.
10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies Zero input-output propagation delay 60 ps typical cycle-to-cycle jitter (high drive) Multiple low skew outputs 85 ps typical output-to-output skew One input drives five outputs (CY2305) One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309) Compatible with Pentium-based systems Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see "Select Input Decoding" on page 3]) Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305) 3.3V operation Industrial temperature available

Logic Block Diagram
PLL
REF
MUX
CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1
S2 Select Input Decoding S1
CLKB2 CLKB3 CLKB4
Cypress Semiconductor Corporation Document #: 38-07140 Rev. *J
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 12, 2009
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CY2305, CY2309
Pinouts
Figure 1. Pin Diagram - CY2305
REF CLK2 CLK1 GND
1 2 3 4 8 7 6 5
CLKOUT CLK4 V DD CLK3
Table 1. Pin Description for CY2305 Pin 1 2 3 4 5 6 7 8 REF
[1]
Signal CLK2[2] CLK1[2] GND CLK3[2] VDD CLK4[2] CLKOUT[2] Buffered clock output Buffered clock output Ground Buffered clock output 3.3V supply Buffered clock output
Description Input reference frequency, 5V tolerant input
Buffered clock output, internal feedback on this pin
Figure 2. Pin Diagram - CY2309
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
Table 2. Pin Description for CY2309 Pin 1 2 3 4 5 6 7 8 9 10 11 12 REF[1] CLKA1[2] CLKA2[2] VDD GND CLKB1[2] CLKB2[2] S2[3] S1[3] CLKB3[2] CLKB4 GND
[2]
Signal Buffered clock output, Bank A Buffered clock output, Bank A 3.3V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground
Description Input reference frequency, 5V tolerant input
Notes 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs.
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CY2305, CY2309
Table 2. Pin Description for CY2309 Pin 13 14 15 16 VDD CLKA3[2] CLKA4
[2] [2]
Signal 3.3V supply Buffered clock output, Bank A Buffered clock output, Bank A
Description
CLKOUT
Buffered output, internal feedback on this pin
Select Input Decoding for CY2309
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-state Driven Driven Driven CLOCK B1-B4 Three-state Three-state Driven Driven CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N
Figure 3. REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Because the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note titled "CY2305 and CY2309 as PCI and SDRAM Buffers."
Note 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
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CY2305, CY2309
Absolute Maximum Conditions
Supply Voltage to Ground Potential................-0.5V to +7.0V DC Input Voltage (Except REF) ............ -0.5V to VDD + 0.5V DC Input Voltage REF .........................................-0.5V to 7V Storage Temperature ................................. -65C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) ........................... > 2,000V
Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter VDD TA CL CL CIN tPU Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min 3.0 0 - - - 0.05 Max 3.6 70 30 10 7 50 Unit V C pF pF pF ms
Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Input HIGH Voltage[5] Voltage[5] VIN = 0V VIN = VDD IOL = 8 mA (-1) IOH = 12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD Test Conditions Min - 2.0 - - - 2.4 - - Max 0.8 - 50.0 100.0 0.4 - 12.0 32.0 Unit V V A A V V A mA
Input LOW Current Input HIGH Current Output LOW Voltage[6]
Output HIGH Voltage[6]
IDD (PD mode) Power Down Supply Current IDD Supply Current
Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices
Parameter[7] t1 tDC t3 t4 t5 t6A Name Output Frequency Duty Cycle[6] = t2 / t1 Rise Time[6] Fall Time[6] Skew[6] Output to Output Test Conditions 30-pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Min 10 10 40.0 - - - - Typ. - 50.0 - - 85 0 Max 100 133.33 60.0 2.50 2.50 250 350 Unit MHz MHz % ns ns ps ps
Delay, REF Rising Edge to CLKOUT Rising Edge[6]
Notes 5. REF input has a threshold voltage of VDD/2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
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CY2305, CY2309
Switching Characteristics for CY2305SC-1 and CY2309SC-1 Commercial Temperature Devices
Parameter[7] t6B Name Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Cycle to Cycle Jitter[6] PLL Lock Time[6] Test Conditions Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Min 1 Typ. 5 Max 8.7 Unit ns
t7 tJ tLOCK
- - -
- 70 -
700 200 1.0
ps ps ms
Switching Characteristics for CY2305SC-1H and CY2309SC-1H Commercial Temperature Devices
Parameter[7] t1 tDC tDC t3 t4 t5 t6A t6B Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Rise Fall Cycle[6] Time[6] Skew[6] = t2 / t1 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout < 50 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Measured at VDD/2 Measured at VDD/2. Measured in PLL Bypass Mode, CY2309 device only. Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Description Min 10 10 40.0 45.0 - - - - 1 Typ. - 50.0 50.0 - - 85 - 5 Max 100 133.33 60.0 55.0 1.50 1.50 250 350 8.7 Unit MHz MHz % % ns ns ps ps ns
Time[6]
Output to Output
Delay, REF Rising Edge to CLKOUT Rising Edge[6] Delay, REF Rising Edge to CLKOUT Rising Edge[6] Device to Device Skew[6] Output Slew Rate[6] Cycle to Cycle Jitter[6] PLL Lock Time[6]
t7 t8 tJ tLOCK
- 1 - -
- - 60 -
700
ps V/ns
200 1.0
ps ms
Operating Conditions for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter VDD TA CL CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100 MHz Load Capacitance, from 100 MHz to 133 MHz Input Capacitance Description Min 3.0 -40 - - - Max 3.6 85 30 10 7 Unit V C pF pF pF
Note 7. All parameters specified with loaded outputs.
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CY2305, CY2309
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter VIL VIH IIL IIH VOL VOH Description Input LOW Voltage[5]
[5]
Test Conditions
Min - 2.0
Max 0.8 - 50.0 100.0 0.4 - 25.0 35.0
Unit V V A A V V A mA
Input HIGH Voltage Input LOW Current
VIN = 0V VIN = VDD IOL = 8 mA (-1) IOH =12 mA (-1H) IOH = -8 mA (-1) IOL = -12 mA (-1H) REF = 0 MHz Unloaded outputs at 66.67 MHz, SEL inputs at VDD
- - - 2.4 - -
Input HIGH Current Output LOW Voltage[6] Output HIGH Voltage[6]
IDD (PD mode) Power Down Supply Current IDD Supply Current
Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter[7] t1 tDC t3 t4 t5 t6A t6B t7 tJ tLOCK Name Output Frequency Duty Cycle[6] = t2 / t1 Rise Time Fall
[6]
Test Conditions 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V Skew[6] All outputs equally loaded
Min 10 10 40.0 - - - - 1 - - -
Typ - 50.0 - - 85 - 5 - 70 -
Max 100 133.33 60.0 2.50 2.50 250 350 8.7 700 200 1.0
Unit MHz MHz % ns ns ps ps ns ps ps ms
Time[6]
Output to Output
Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT Rising Edge[6] CY2309 device only. Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins of devices Cycle to Cycle PLL Lock Jitter[6] Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin Time[6]
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Parameter[7] t1 tDC tDC t3 t4 t5 t6A t6B t7 Name Output Frequency Duty Cycle[6] = t2 / t1 Duty Rise Cycle[6] Time[6] Skew[6] = t2 / t1 30 pF load 10 pF load Measured at 1.4V, Fout = 66.67 MHz Measured at 1.4V, Fout < 50 MHz Measured between 0.8V and 2.0V Measured between 0.8V and 2.0V All outputs equally loaded Description Min 10 10 40.0 45.0 - - - - 1 - Typ - 50.0 50.0 - - 85 - 5 - Max 100 133.33 60.0 55.0 1.50 1.50 250 350 8.7 700 Unit MHz MHz % % ns ns ps ps ns ps
Fall Time[6] Output to Output
Delay, REF Rising Edge to Measured at VDD/2 CLKOUT Rising Edge[6] Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT Rising Edge[6] CY2309 device only. Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins of devices
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CY2305, CY2309
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Parameter[7] t8 tJ tLOCK Name Output Slew Rate
[6]
Description Measured between 0.8V and 2.0V using Test Circuit #2 Measured at 66.67 MHz, loaded outputs Stable power supply, valid clock presented on REF pin
Min 1 - -
Typ - 60 -
Max - 200 1.0
Unit V/ns ps ms
Cycle to Cycle Jitter[6] PLL Lock Time
[6]
Switching Waveforms
Figure 4. Duty Cycle Timing
t1 t2 1.4V 1.4V 1.4V
Figure 5. All Outputs Rise/Fall Time
3.3V 0V
OUTPUT
2.0V 0.8V t3
2.0V 0.8V t4
Figure 6. Output-Output Skew
1.4V
OUTPUT
OUTPUT t5
1.4V
Figure 7. Input-Output Propagation Delay
VDD/2
INPUT
OUTPUT t6
VDD/2
Figure 8. Device-Device Skew
VDD/2
CLKOUT, Device 1
CLKOUT, Device 2 t7
VDD/2
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CY2305, CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1 and CY2309-1
Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% )
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% ) 54 52 50 48 46 44 42 40 33 MHz 66 MHz 100 MHz 133 MHz
54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz
3
3.1
3.2
3.3 VDD (V)
3.4
3.5
3.6
Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V)
60 58 56 Duty Cycle (%)
Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V)
60 58 56 Duty Cycle (%)
-40C 0C 25C 70C 85C
54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
-40C 0C 25C 70C 85C
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
140 120 100 IDD (mA) 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 33 MHz 66 MHz 100 MHz
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
140 120 100 IDD (mA) 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 33 MHz 66 MHz 100 MHz
Notes 8. Duty cycle is taken from typical chip measured at 1.4V. 9. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V); f = frequency (Hz)).
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CY2305, CY2309
Typical Duty Cycle[8] and IDD Trends[9] for CY2305-1H and CY2309-1H
Duty Cycle Vs VDD (for 30 pF Loads over Frequency - 3.3V, 25C)
60 58 56 Duty Cycle (% ) Duty Cycle (% ) 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 60 58 56 54 52 50 48 46 44 42 40 3 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6 33 MHz 66 MHz 100 MHz 133 MHz
Duty Cycle Vs VDD (for 15 pF Loads over Frequency - 3.3V, 25C)
Duty Cycle Vs Frequency (for 30 pF Loads over Temperature - 3.3V)
60 58 56 Duty Cycle (%)
Duty Cycle (%)
Duty Cycle Vs Frequency (for 15 pF Loads over Temperature - 3.3V)
60 58 56
54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
-40C 0C 25C 70C 85C
54 52 50 48 46 44 42 40 20 40 60 80 Frequency (MHz) 100 120 140
-40C 0C 25C 70C 85C
IDD vs Number of Loaded Outputs (for 30 pF Loads over Frequency - 3.3V, 25C)
160 140 120 IDD (mA) 33 MHz 66 MHz 100 MHz IDD (mA) 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 # of Loaded Outputs 160 140 120 100 80 60 40 20 0 0 1
IDD vs Number of Loaded Outputs (for 15 pF Loads over Frequency - 3.3V, 25C)
33 MHz 66 MHz 100 MHz
2
3
4
5
6
7
8
9
# of Loaded Outputs
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CY2305, CY2309
Test Circuits
Test Circuit # 1 V DD 0.1 F CLK OUTPUTS C LOAD V DD 0.1 F GND GND 0.1 F V DD GND GND out 0.1 F Test Circuit # 2 V DD OUTPUTS 10 pF 1 k 1 k
For parameter t8 (output slew rate) on -1H devices
Ordering Information for CY2305
Ordering Code CY2305SC-1[10] CY2305SC-1T[10] CY2305SI-1[10] CY2305SI-1T[10] CY2305SC-1H[10] CY2305SC-1HT[10] CY2305SI-1H[10] CY2305SI-1HT[10] Pb-Free CY2305SXC-1 CY2305SXC-1T CY2305SXI-1 CY2305SXI-1T CY2305SXC-1H CY2305SXC-1HT CY2305SXI-1H CY2305SXI-1HT 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel 8-pin 150-mil SOIC 8-pin 150-mil SOIC - Tape and Reel Package Type Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial
Ordering Information for CY2309
Ordering Code CY2309SC-1
[10]
Package Type 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC
Operating Range Commercial Commercial Industrial Industrial Commercial
CY2309SC-1T[10] CY2309SI-1[10] CY2309SI-1T[10] CY2309SC-1H[10]
Note 10. Not recommended for new designs.
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CY2305, CY2309
Ordering Information for CY2309 (continued)
Ordering Code CY2309SC-1HT CY2309ZC-1H CY2309SI-1H Pb-Free CY2309SXC-1 CY2309SXC-1T CY2309SXI-1 CY2309SXI-1T CY2309SXC-1H CY2309SXC-1HT CY2309SXI-1H CY2309SXI-1HT CY2309ZXC-1H CY2309ZXC-1HT CY2309ZXI-1H CY2309ZXI-1HT 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP - Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP - Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial CY2309ZC-1HT CY2309SI-1HT
[10] [10] [10]
Package Type 16-pin 150-mil SOIC - Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel
Operating Range Commercial Commercial Commercial Industrial Industrial
[10] [10]
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CY2305, CY2309
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S08 8-Pin (150-Mil) SOIC S8 Figure 8.
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
51-85066-*C
0.0138[0.350] 0.0192[0.487]
16 Lead (150 Mil) SOIC
Figure 9. 16-Pin (150-Mil) SOIC S16
PIN 1 ID
8
1 DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
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CY2305, CY2309
Package Drawing and Dimensions (continued)
Figure 10. 16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05gms
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027]
51-85091-*A
4.90[0.193] 5.10[0.200]
0.09[[0.003] 0.20[0.008]
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CY2305, CY2309
Document History Page
Document Title: CY2305/CY2309 Low Cost 3.3V Zero Delay Buffer Document Number: 38-07140 Rev. ** *A ECN 110249 111117 Orig. of Change SZV CKN Submission Date 10/19/01 03/01/02 Description of Change Change from Spec number: 38-00530 to 38-07140 Added t6B row to the Switching Characteristics Table; also added the letter "A" to the t6A row Corrected the table title from CY2305SC-IH and CY2309SC-IH to CY2305SI-IH and CY2309SI-IH Added eight-pin TSSOP packages (CY2305ZC-1 and CY2305ZC-1T) to the ordering information table. Added the Tape and Reel option to all the existing packages: CY2305SC-1T, CY2305SI-1T, CY2305SC-1HT, CY2305SI-1HT, CY2305ZC-1T, CY2309SC-1T, CY2309SI-1T, CY2309SC-1HT, CY2309SI-1HT, CY2309ZC-1HT, CY2309ZI-1HT Power up requirements added to Operating Conditions information Added Lead-free for all the devices in the ordering information table Added a Lead-free with the new coding for all SOIC devices in the ordering information table Added TSSOP Lead-free devices Added typical values for jitter Updated template. Added Note "Not recommended for new designs." Added part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed part number CY2305SZC-1, CY2305SZC-1T, CY2305SZI-1, CY2305SZI-1T, CY2305SZC-1H, CY2305SZC-1HT, CY2305SZI-1H, CY2305SZI-1HT, CY2309SZC-1, CY2309SZC-1T, CY2309SZI-1, CY2309SZI-1T, CY2309SZC-1H, CY2309SZC-1HT, CY2309SZI-1H, CY2309SZI-1HT, CY2309ZZC-1H, CY2309ZZC-1HT, CY2309ZI-1H, CY2309ZI-1HT, CY2309ZZI-1H, and CY2309ZZI-1HT in Ordering Information table. Changed Lead-Free to Pb-Free. Removed part number CY2305ESXC-1, CY2305ESXC-1T, CY2305ESXI-1, CY2305ESXI-1T, CY2305ESXC-1H, CY2305ESXC-1HT, CY2305ESXI-1H, CY2305ESXI-1HT, CY2309ESXC-1, CY2309ESXC-1T, CY2309ESXI-1, CY2309ESXI-1T, CY2309ESXC-1H, CY2309ESXC-1HT, CY2309ESXI-1H, CY2309ESXI-1HT, CY2309EZXC-1H, CY2309EZXC-1HT, CY2309EZXI-1H, and CY2309EZXI-1HT in ordering information table. Removed note references to note 10 in Pb-Free sections of ordering information table. Changed IDD (PD mode) from 12.0 to 25.0 A for commercial temperature devices Deleted Duty Cycle parameters for Fout < 50 MHz commercial and industrial devices. Reverted IDD (PD mode) and Duty Cycle parameters back to the values in revision *H: Changed IDD (PD mode) from 25 to 12 A for commercial devices. Added Duty Cycle parameters for Fout < 50 MHz for commercial and industrial devices.
*B
117625
HWT
10/21/02
*C *D *E *F *G *H
121828 131503 214083 291099 390582 2542461
RBI RGL RGL RGL RGL AESA
12/14/02 12/12/03 See ECN See ECN See ECN 07/23/08
*I
2565153
AESA
09/18/08
*J
2673353
KVM/PYRS
03/13/09
Document #: 38-07140 Rev. *J
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(c) Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07140 Rev. *J
Revised March 12, 2009
Page 15 of 15
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